1. Field of the Invention
The invention generally relates to digital communications. In particular, the invention relates to equalization techniques in a receiver.
2. Description of the Related Art
A variety of physical impairments can limit the effective transmission of data signals over communications channels. For example, the frequency selective nature of a communication channel attenuates and phase shifts the various frequency components of an input signal differently depending on frequency. A corresponding impulse response can span several symbol intervals, which can result in time smearing and interference between successive transmitted input symbols, which is known as inter-symbol interference (ISI). The ISI resulting from the channel distortion, if left uncompensated, can undesirably result in relatively high error rates. One approach to the ISI problem is to have a receiver compensate or reduce the ISI in the received signal with an equalizer.
There are two general classes of equalization techniques to mitigate ISI: (a) Maximum likelihood sequence estimation (MLSE) techniques and (b) sub-optimal equalizer structures.
With maximum likelihood sequence estimation (MLSE) techniques, a dynamic programming algorithm is used to determine the most likely transmitted sequence given observations of the received noisy and ISI-corrupted sequence, and given knowledge of the channel impulse response coefficients. MLSE techniques use a sequence of received signal samples over successive symbol intervals to make decisions about the transmitted symbols, and MLSE techniques are optimal from a bit error rate (BER) perspective. However, MLSE techniques have a computational complexity that grows exponentially with the length of the channel time dispersion, and in most channels of practical interest, such a large computational complexity can be prohibitively expensive to implement.
Examples of sub-optimal equalizer structures include a linear equalizer (LE) and a decision feedback equalizer (DFE). With a linear equalizer (LE) or with a decision feedback equalizer (DFE), data detection is performed on a symbol-by-symbol basis and hence can be much simpler to implement than with maximum likelihood sequence estimation MLSE techniques. See, for example, Proakis, John G., Digital Communications, McGraw-Hill, (3rd Edition 1995), U.S. Pat. No. 5,058,130 to Park and U.S. Pat. No. 6,414,990 B1 to Jonsson et al.
In a linear equalizer (LE), a simple finite impulse response (FIR) filter is used to mitigate ISI. A linear equalizer (LE) uses a linear filter with adjustable or fixed coefficients.
In a decision feedback equalizer (DFE), in addition to the feed-forward FIR filter of the linear equalizer (LE), the DFE uses a feedback filter (FBF) with the previously detected symbols. The feedback filter (FBF) of the DFE suppresses that part of the inter-symbol interference (ISI) from the present estimate caused by previously detected symbols. A DFE typically yields a significant improvement in performance relative to a linear equalizer (LE) having the same number of taps when the channel frequency response is severely distorted. Advantages of a decision feedback equalizer (DFE) over a linear equalizer (LE) include compensation for channel distortions without as much noise enhancement and less sensitive performance to the sampler phase.
Decision Feedback Equalizer (DFE) Example (FIG. 1)
A decision feedback equalizer (DFE) can be incorporated in a receiver in a broad variety of ways. FIG. 1 illustrates an example of a typical configuration of a receiver of a digital communications system, where the decision feedback equalizer (DFE) is decoupled from the symbol synchronization. In FIG. 1, the decision feedback equalizer (DFE) includes a feed forward filter (FF filter), a differencing or subtracting circuit, a slicer, and a feedback filter (FB filter).
In the simple receiver of FIG. 1, analog signal processing of the received signal xA(t) is used to derive a (symbol timing) clock signal. This clock signal is used to sample the received signal xA(t) and to produce a discrete signal xD(nT), which is provided as an input to the decision feedback equalizer (DFE). Feed-forward filter (FF filter) generates an output signal xDf(nT) relatively free of the pre-cursor inter-symbol interference (ISI) terms present in the discrete signal xD(nT). The feedback filter (FB filter) uses the previously detected symbol sequence, i.e., hard decision output d(nT), to generate recreated signal zD(nT), which contains the post-cursor ISI terms. The recreated signal zD(nT) is subtracted from the discrete signal xDf(nT) to generate a soft equalizer output signal yD(nT), which is relatively free from ISI and is provided as an input to the slicer to make the final decisions about the transmitted symbol sequence.
The timing phase of the received signal xA(t) can be estimated using the zero-crossing time of the received signal xA(t). Fluctuations in the zero-crossings of the received signal xA(t) can render the phase of the clock signal unstable, which decreases the error performance of the receiver. There are different approaches to overcome this problem. One approach is to use a phase locked loop with a very narrow loop bandwidth. Another approach is to move the operation of the decision feedback equalizer (DFE) to the analog domain and arrange the taps of the DFE to minimize jitter rather than minimize ISI at the sampling point. For example, see U.S. Pat. No. 5,058,130. Another approach is to couple the timing phase estimation with the equalizer by providing the hard decision output d(nT) as an input to the timing phase estimation, see Proakis. Another approach is to arrange the taps of the DFE to optimize a cost function associated with the performance of the equalizer structure, see U.S. Pat. No. 6,414,990. One drawback of these techniques is their increased complexity.
Digital DFE with Feedback Filter Only (FIG. 2)
When the pre-cursor inter-symbol interference (ISI) terms of the channel impulse response are relatively small, the feed forward filter (FF filter) portion of the decision feedback equalizer (DFE) of the receiver illustrated in FIG. 1 can be omitted as illustrated in the receiver configuration of FIG. 2. The feedback filter (FB filter) is retained to remove post-cursor inter-symbol interference (ISI).
In the receiver illustrated in FIG. 2, the received analog signal xA(t) is sampled with an n-bit analog-to-digital converter (ADC) to generate a discrete signal xD(nT). The samples of the discrete signal xD(nT) are provided as an input to the subtractor, where the inter-symbol interference (ISI) is cancelled by subtraction with the recreated signal zD(nT), producing the soft decision feedback equalizer (DFE) output signal yD(nT). The slicer receives the soft DFE output signal yD(nT) as an input, and the slicer generates the hard decision output sequence d(nT) as an output. The coefficients of the feedback filter hk(k=1, . . . , n) represent the post-cursor samples of the overall channel impulse response and may be obtained in a variety of ways. When the corresponding impulse response of the channel is relatively well known, the coefficients hk may be predetermined and fixed to the corresponding values. Or, for channels of unknown characteristic or for adaptive modes of operation, the coefficients can be computed using an algorithm such as least-mean-squares (LMS).
In a relatively high-speed base-band transmission system, such as 5 Gbit/s systems or faster systems employing high-speed SerDes devices, the n-bit ADC converter described in the receiver configuration illustrated in FIG. 2 can be very expensive and can be economically impractical. To avoid the usage of high-speed n-bit ADCs, the sampling function can be moved to the slicer block. FIG. 3 illustrates a model of this analog implementation of the decision feedback equalizer (DFE).
Model 1 of the DFE Analog Implementation (FIG. 3)
FIG. 3 illustrates a first model of a decision feedback equalizer (DFE) of a receiver configuration. The subtracting circuit operates in the analog domain. A corresponding data eye will be described later in connection with FIG. 6. A corresponding timing diagram will be described later in connection with FIG. 7.
In the model illustrated in FIG. 3, while both the sampling of an equalized signal yA(t) and a zero-order-hold (ZOH) performed on the recreated signal zD(nT) are explicitly drawn, it will be understood that the sampling of the equalized signal yA(t) to the soft equalizer output signal yD(nT), and the zero-order-hold (ZOH) performed can be implicit in the operation of the slicer and feedback filter (FBF), respectively. The explicit blocks are illustrated to emphasize the analog nature of the subtracting circuit as opposed to the digital subtracting circuits illustrated in FIG. 1 and FIG. 2.
The zero-order-hold (ZOH) of the feedback filter (FBF) holds the analog signal zDA(t) constant during the symbol interval T and changes the value abruptly at the sampling instants. In this manner, the feedback filter is similar to a digital-to-analog converter (DAC).
In some applications, the received signal xA(t) may be fractionally sampled, i.e., sampled at a higher rate than the symbol rate, and passed to the decision feedback equalizer (DFE) of the receiver model illustrated in FIG. 3. Both the illustrated digital implementation and a true analog implementation of a decision feedback equalizer (DFE) are referred to as a decision feedback equalizer (DFE) herein.
In a practical true analog implementation of DFE, the first flip-flop in the delay buffer of the feedback filter (FBF) typically performs three tasks: sampling, slicing and delay. Hence, a model illustrated in FIG. 4 also describes the operation of an decision feedback equalizer (DFE).
Model 2 of the DFE Analog Implementation (FIG. 4)
FIG. 4 illustrates a second model (model 2) of a decision feedback equalizer (DFE) of a receiver configuration. A corresponding data eye diagram for the second model will be described later in connection with FIG. 8, and a corresponding timing diagram will be described later in connection with FIG. 9. The first delay T of the feedback filter (FBF) of model 1 is not present in model 2. Model 2 includes a delay τ1 that represents a flip-flop propagation delay within the slicer. The flip-flop propagation delay τ1 corresponds to a value between 0 and T (0<τ1<T).
Simulated Data Eye Diagram of the Received Signal xA(t) (FIG. 5)
When a transmission channel introduces significant amounts of inter-symbol interference (ISI), the associated system performance can be relatively poor when a simple clock recovery unit based on the zero-crossings of the received signal is employed in the receiver. This often happens with base-band high-speed signaling (>5 Gbit/s) over back-plane channels that create mostly post-cursor ISI terms.
FIG. 5 is a simulated example of a data eye diagram of non-return to zero (NRZ) signaling at 5 Gbit/s over a typical 30-inch channel for the received signal xA(t) with relatively large amounts of inter-symbol interference (ISI). A “data eye” corresponds to superimposed waveforms for binary bits of “0” and “1” within a bit period. FIG. 5 illustrates two data eyes of two successive bit (symbol) intervals. Bold vertical lines at about 1×10−10 and 3×10−10 seconds illustrate relatively good decision points for a slicer (or for sampling for the slicer). In one embodiment, these relatively good decision points are approximately in the middle of a symbol interval.
As illustrated by the data eye diagram of FIG. 5, the zero-crossing variation (crossings over or under 0 amplitude) due to inter-symbol interference (ISI) is large enough to produce a significant amount of jitter. This can be problematic when techniques such as an early-late gate synchronizer are used without sufficient averaging. Consequently, bit-error-rate (BER) performance of the system will tend to be relatively low.
When the received signal xA(t) corresponding to the data eye diagram of FIG. 5 is equalized with a decision feedback equalizer (DFE) structure as illustrated in FIG. 3, the DFE cancels the inter-symbol interference (ISI) terms relatively well typically only at sampling points. Furthermore, the discrete time nature of analog signal zDA(t) introduces jumps (discontinuities) in the equalized signal yA(t) at the sampling instants as illustrated in simulated example of FIG. 6.
Simulated Data Eye Diagram at the Slicer Input After Applying Model 1 of Conventional DFE (FIG. 6)
The data eye diagram for the slicer input corresponds to the equalized signal yA(t) of FIG. 3. In the simulated example of FIG. 6, the corresponding receiver (modeled earlier in FIG. 3) uses a decision feedback equalizer (DFE) that cancels all post-cursor ISI terms. The two distinct levels at the sampling instants (1×10−10 and 3×10−10 seconds in FIG. 6) are the consequence of the single dominant pre-cursor term of the simulated channel.
As illustrated by the data eyes in FIG. 6, the first half, e.g., between 0×10−10 and 1×10−10 seconds, of the symbol interval is relatively corrupted while the second half, e.g., between 1×10−10 and 2×10−10 seconds, is relatively clean. This is explained further by the timing diagram illustrated in FIG. 7 for the decision feedback equalizer (DFE) described earlier in connection with FIG. 3.
Operation of a Conventional DFE Using Model 1 (FIG. 7)
Five signals relevant to the description of the operation of the decision feedback equalizer (DFE) are presented in FIG. 7: transmitted signal sequence s(t), received clock signal rx_clk, equalized signal yA(t), slicer output signal d(t) and delayed slicer output signal d(t−T). The transmitted signal sequence s(t) corresponds to the symbol sequence carried by the received signal xA(t). The slicer output d(t) corresponds to the continuous time observation of the otherwise discrete time hard decision output d(nT). The delayed slicer output signal d(t−T) is a continuous time representation of the first delay T of the feedback filter (FBF). The delayed slicer output signal d(t−T) is time delayed by a symbol period from the slicer output d(t) and is used in the feedback filter (FBF) to cancel the post-cursor inter-symbol interference (ISI) from the previously detected symbol.
Three successive symbol intervals are marked as A, B and C representing the current symbol (C) and two previous symbols (A and B). For clarity, the example is illustrated assuming that the channel characteristic is such that only one post-cursor inter-symbol interference (ISI) component is created, e.g., the inter-symbol interference (ISI) in symbol C is a result only of transmission of symbol B.
Furthermore, in this simulated example, zero channel delay is used, i.e., transmitted signal sequence s(t) and equalized signal yA(t) are perfectly aligned in time as shown in the figure. The received signal xA(t) of FIG. 3 is also perfectly aligned with equalized signal yA(t) in the simulation.
In this example, the slicer determines the symbols of the transmitted data at the peaks of equalized signal yA(t), and the slicer output d(t) is delayed by half a symbol period with respect to transmitted signal sequence s(t). After that, the delayed slicer output signal d(t−T) will be properly weighted in the feedback filter and subtracted from the received signal xA(t) in order to produce the equalized signal yA(t).
Due to a half symbol delay at the slicer, only the second half of current symbol C carried by the equalized signal yA(t) overlaps with the interfering previous symbol B portion of the delayed slicer output signal d(t−T), while the first half of the current symbol C overlaps with the symbol A portion of the delayed slicer output signal d(t−T).
The inter-symbol interference (ISI) term from symbol B has been effectively cancelled in the equalized signal yA(t) only at the sampling instants because the received signal xA(t), from which the equalized signal yA(t) is generated, is an analog signal with varying analog voltage levels during a symbol interval. As time proceeds from a sampling point (moving to the right in FIG. 6), the inter-symbol interference (ISI) cancellation error in the equalized signal yA(t) increases. The ISI cancellation error is even larger earlier in time to a sampling instant (to the left of a sampling instant in FIG. 6) because prior to the sampling instant, the canceling term is based on previous symbol A instead of previous and interfering symbol B. For this reason, equalized signal yA(t) exhibits the data eye illustrated in FIG. 6.
However, if the received signal xA(t) is equalized with a decision feedback equalizer (DFE) structure corresponding to the model illustrated FIG. 4, the resulting data eye diagram exhibits discontinuous behavior as illustrated in FIG. 8.
Simulated Eye Diagram at the Slicer Input After Applying Model 2 of Classical DFE (FIG. 8)
The data eye diagram for the slicer input corresponds to the equalized signal yA(t) of FIG. 4. In contrast to the behavior of the decision feedback equalizer (DFE) behavior according to model 1 and FIGS. 3, 6, and 7, the DFE according to model 2 exhibits nearly the opposite characteristics. The DFE according to model 2 was previously described earlier in connection with FIG. 4. The data eye diagram in FIG. 8, and a timing diagram in FIG. 9 also correspond to the DFE according to model 2. In the data eye diagram of FIG. 8, the second half, e.g., 1×10−10 and 2×10−10 seconds of the symbol interval is relatively corrupted while the first half of the symbol interval, e.g., 0×10−10 and 1×10−10 seconds is relatively clean.
Operation of a Conventional DFE Using Model 2 (FIG. 9)
The behavior of a DFE according to model 2 will now be described with reference to the timing diagram of FIG. 9. Four signals relevant to the description of the operation of the decision feedback equalizer (DFE) are presented in FIG. 9: transmitted signal sequence s(t), received clock signal rx_clk, equalized signal yA(t), and slicer output signal d(t−τ1).
As illustrated in FIG. 9, the slicer output signal d(t−τ1) is offset in time from the equalized signal yA(t). The offset τ1 can be arbitrary and represents the propagation delay of the first flip-flop, which, for an ideal flip-flop, approaches 0. It will be understood, however, that with relatively high bit rates, the propagation delay τ1 can be relatively large and should not be ignored. The slicer output signal d(t−τ1) is used in the feedback filter (FBF) to cancel the post-cursor inter-symbol interference (ISI) from the previously detected symbol.
Three successive symbol intervals are indicated as A, B, and C representing the current symbol (A) and two previous symbols (B and C). For clarity, the simulated channel characteristic is such that only one post-cursor inter-symbol interference (ISI) component is created (the ISI in present symbol C is a result only of transmission of symbol B).
The slicer determines the symbols of the transmitted data at the peaks of equalized signal yA(t). The slicer output signal d(t−τ1) is weighted in the feedback filter by the coefficients h1, h2, . . . hn, illustrated in FIG. 4 and subtracted from the received signal xA(t) to produce the equalized signal yA(t).
Due to a delay at the slicer, the first half of the symbol C portion of equalized signal yA(t) plus a delay τ1 (flip-flop propagation delay) overlaps with the interfering prior symbol B of the slicer output signal d(t−τ1), while the second half minus the delay τ1 overlaps with a portion of symbol C from the slicer output signal d(t). In a case with ideal components where the flip-flop propagation delay τ1 approaches 0, the “clean” and “corrupted” intervals are each T/2.
The inter-symbol interference (ISI) term from prior symbol B has been effectively cancelled in the equalized signal yA(t) only at the sampling instants, e.g., 1.0×10−10 and 3.0×10−10 seconds, because the received signal xA(t), from which the equalized signal yA(t) is generated, is an analog signal with varying analog voltage levels during a symbol interval. Earlier in time to the sampling points (to the left in FIG. 9), the ISI cancellation error in equalized signal yA(t) increases. Shortly after the sampling instants (to the right in FIG. 9), the ISI cancellation error is relatively large because the canceling term is based on current symbol C instead of previous and interfering symbol B. As a result, the equalized signal yA(t) exhibits the data eye illustrated in FIG. 8.